Semiconductor manufacturing involves the printing of multiple integrated circuit patterns on successive levels of exposure tools known as steppers. These steppers typically pattern different layers by applying step and repeat lithography exposure or step and scan lithography exposure in which the full area of a wafer is patterned by the sequential exposure of stepper fields containing one or more integrated circuits (also known as chips).
A requirement of the manufacturing process is to keep the alignment error, between levels, below acceptable product tolerances. FIGS. 1a, 1b, 1c, 1d, and 1e show qualitative examples of possible field alignment errors for four adjacent fields. Specifically, FIG. 1a shows field rotation about the center; FIG. 1b shows no field errors; FIG. 1c shows X,Y translation in which all of the fields on the substrate are shifted by the same amount in the X (horizontal) and Y (vertical) directions; FIG. 1d shows X,Y field magnification (i.e., the stepped fields are too small or too large); and FIG. 1e shows field skew. FIGS. 2a, 2b, and 2c show qualitative examples of possible field grid overlay errors which can result after applying the exposure systems. Specifically, FIG. 2a shows X,Y grid magnification (i.e., the fields are stepped too far apart between the "A" and the "B" levels); FIG. 2b shows grid rotation in which all of the patterns on the "B" level are rotated with respect to the patterns on the "A" level; and FIG. 2c shows grid skew.
A conventional method used to measure and control intra-field error is shown in FIGS. 3a and 3b. The "A" to "A" (or "B" to "B") type overlay errors are between-field errors that occur within a single level to itself. A single field 56 is shown in FIG. 3a having outer boxes 52 on the left and top side and inner boxes 54 on the bottom and right. Outer boxes 52 are larger than inner boxes 54. When multiple fields are stepped adjacent to one another, the two sets of boxes interlock with inner boxes 54 positioned in outer boxes 52 as shown in FIG. 3b. Metrology tools are used to measure the overlay error based on how far the inner box 54 is displaced from the center of the outer box 52. Metrology refers to measurement of the relative X and Y center displacement differences between the interlocking box-in-box structures 50 for the purposes of the drawing. Metrology can also be accomplished by other techniques; the present invention does not depend on the specific overlay measurement technique used.
Because inner boxes 54 are centered in outer boxes 52 as shown in FIG. 3b, no between-field error exists. FIG. 4 provides a qualitative example of field rotation error where the interlocking box-in-box structures 50 are displaced (i.e., inner boxes 54 are translated upward and to the right relative to outer boxes 52). FIG. 5 similarly provides a qualitative example of field Y magnification error where the interlocking box-in-box structures 50 are also displaced but in a different way.
A conventional method used to control level-to-level error is shown in FIGS. 6a, 6b, and 6c. The "B" to "A" type overlay errors occur between two overlying levels "A" and "B" FIG. 6a shows "B" level pattern 60 surrounded by outer boxes 62. FIG. 6b shows "A" level pattern 66 surrounded by inner boxes 64. Outer boxes 62 are larger than inner boxes 64. "B" level pattern 60 is placed over "A" level pattern 66 (as shown by the arrow 68) to yield the result 70 shown in FIG. 6c. As above, metrology tools are used to measure the overlay error based on how far the inner box 64 is displaced from the center of the outer box 62. Because inner boxes 64 are centered in outer boxes 62 as shown in FIG. 6c, no level-to-level error exists.
The typical process flow diagram used to correct and align an overlay system at the N.sup.th level, where two different photo tools are used, is shown in FIG. 7. U.S. Pat. No. 5,444,538 issued to Pelligrini teaches a system and method for optimizing the grid and level-to-level registration of wafer patterns. It is an example of "B" to "A" level control using two different photo tools. Pelligrini specifically addresses the equations and solutions for a two field on one field overlay system.
The conventional solution is insufficient to allow field size mixing between large field and small field applications due to the random walk accrual of incremental field error. A method of minimization of overlay error is needed for cross-boundary stepping applications in which the fields on successive levels straddle the boundaries between fields on each level.